A level shifting circuit is widely applied in various interface circuits and input and output units, for implementing logic shifting of a level. FIG. 1 is a schematic structural diagram of a circuit for implementing level shifting in design for an integrated circuit. The level shifting circuit is generally used for shifting a logic level from a ground level GND to a positive power supply VDD to a logic level from a negative power supply VNEG to the positive power supply VDD. For example, a voltage ranging from 0 to 2.5 V may be shifted to a voltage ranging from −2.5 to 2.5 V. Referring to FIG. 1, the level shifting circuit includes 16 Metal-Oxide Semiconductor Field Effect Transistors (MOS-FET), which are respectively represented as M1 to M16. M1 to M4 are MOS transistors for shifting the level. M5-M8, as buffer structures, may have high current driving capability. M9 to M16 share a high voltage between a positive voltage VDD and the negative power supply VNEG so as to avoid overvoltage of the MOS transistors.
The circuit structure for implementing level shifting in the design for the integrated circuit is simply introduced above. An operation principle of the level shifting circuit is described in detail below. In a case that an input level signal Sp is a ground level GND, since a voltage between a source electrode and a gate electrode of M4 is greater than a threshold voltage Vthp of a PMOS transistor, M4 is switched on. A source voltage of M12 increases due to the switch-on of M4, and a voltage between a source electrode and a gate electrode of M12 is greater than a threshold voltage Vthp of the PMOS transistor, and thus the M12 is switched on. A drain voltage of M10 is increased due to the switch-on of the M4 and M12, since the voltage between a gate electrode of M10 and a source electrode of M2 is a difference between the ground level GND and the negative power supply VNEG, an equivalent capacitance is between a gate electrode and a source electrode of M10, an equivalent on-resistance or off-capacitance is between a drain electrode and a source electrode of M2. A voltage is shared between the gate electrode and the source electrode of M10, and the voltage is higher than a threshold voltage Vthn of a NMOS and is large enough to switch on M10. Further, M1, M2, M5 and M6 are initially in switch-off states, a current path formed by the switch-on of M4, M12 and M10 charges gate electrodes of M1 and M6, so as to enable M1 and M6 be switched on. Gate voltages of M5 and M2 decrease due to the switch-on of M1, so as to enable M5 and M2 to be switched off and keep M2 in a switch-off state. A source voltage of M14 decreases due to the switch-on of the M6, to enable a voltage between a gate electrode and a source electrode of M14 to be higher than the threshold voltage Vthn of the NMOS, and M14 is switched on. M8 is in the switch-off state due to an inverted signal Sn of Sp. In this case, an output signal Vp is the negative power supply VNEG. Similarly, in a case that the input level signal Sp is the positive power supply VDD, an output voltage signal Vp is the positive power supply VDD. It can be known from the operation principle analyzed above that with the level shifting circuit, the logic level from the ground level GND to the positive power supply VDD is shifted to a logic level from a negative power supply VNEG to the positive power supply VDD.
However, due to simultaneous shifting of the level signals during the process of shifting the input level signal Sp, M1 and M3 may be simultaneously switched on, M2 and M4 may be simultaneously switched on, M5 and M7 may be simultaneously switched on, M6 and M8 may be simultaneously switched on, and further a loop is generated between the positive power supply VDD and the negative power supply VNEG, resulting in electric leakage. Therefore, not only more dynamic current is consumed, but also more glitches are produced on edges of output voltage signal, and it is difficult to provide a control level with high quality to a post-stage circuit.